As illustrated by FIG. 1, an overlay structure typically includes an emitter stripe with a base contact situated outside of the emitter stripe on either side thereof. The base contacts are fed inwards into the middle of the emitter. On most overlay devices in general use, a polyconductor stripe covers the emitter and makes contact to the emitter. By offsetting this contact in a succeeding layer, a lateral ballasting effect is obtained. This offset may be obtained by placing a polyresistor layer between the contact and the polyresistor stripe. Current then flows through the contact, through the polyresistor layer, and into the emitter contact.
It is known in the semiconductor art that figures of merit may be used to describe the performance of a semiconductor device. One figure of merit of particular interest is defined as the numerical ratio between the emitter periphery (EP) and the base area (BA).
In a semiconductor device operating at high frequencies, low capacitance and hence high current handling capability is particularly desirable. Furthermore, high current handling capability results in high power capability. In order to design a high power, low capacitance device, the emitter periphery is increased as much as possible and the base area is decreased as much as possible. By increasing emitter periphery and decreasing base area, the figure of merit of the device is increased.
High-current handling transistors are subject to the phenomenon of second breakdown. Second breakdown occurs when, due to a non-uniform current distribution over the emitter zones ("current crowding") the temperature locally increases, as a result of which an avalanche effect is produced which leads to local current concentration and finally to destruction of the transistor.
In order to avoid this, the emitter zones are provided with emitter series resistors, also designated as ballast or stabilization resistors. These resistors ensure that a uniform distribution of the current over the various emitter zones is obtained due to the fact that upon increase of the current across an emitter zone the voltage drop across the series resistor connected thereto increases, as a result of which the current through this emitter zone decreases.
Various methods are known by which these emitter series resistors can be realized. For example, U.S. Pat. No. 3,896,475 discloses a well known method, according to which a common strip-shaped semiconductor resistance region of the same conductivity type as the base zone is used, which forms a pn junction with the collector region. The series resistor associated with a given emitter zone is then formed by the material of the resistance region present between the connection with the relevant emitter electrode and the connection with the connection conductor. By increasing the dimensions of the resistance region, the ballast resistance in turn is increased.
Although, it may be desirable to increase the ballast resistance of a device, increasing ballast resistance by increasing the dimensions of the resistance region may have undesirable effects. In particular, to increase the frequency handling capability of a device, the base dimensions may require minimization in order to increase the current handling capability of the device. This is accomplished by reducing the base area of the device to obtain a higher figure of merit. Unfortunately, this reduction results in inadequate room to include ballasting. In other words, by increasing the figure of merit, the maximum ballasting achievable is reduced. Conversely, by increasing the ballasting in a device, the figure of merit decreases.